24-hour chip design cycle called possible

August 8, 2001 | Source: EE Times

A new “chip-in-a-day” method could cut system-on-chip design time from months to 24 hours.The Berkeley Wireless Research Center (BWRC) claims the method be two to three orders of magnitude more efficient in power and area than previous architectures.

Bob Brodersen, professor of electrical engineering and computer science at the University of California, Berkeley, and BWRC’s scientific director, said the center’s methodology could result in “much faster transitioning of really high-performance algorithms into the real world.” It will probably take six more months to hone the process, but after that, commercial adoption could follow “pretty quickly.”