The chip comprises three or more processors stacked vertically and connected together. resulting in increased speed and multitasking, more memory and calculating power, better functionality, and wireless connectivity (credit: EPFL/Alain Herzog)

EPFL scientists are developing an industry-ready prototype of a 3D chip and high-performance, reliable manufacturing method intended to reduce interconnect length (distance between chip circuits) and speed up data exchange.

The chip comprises three or more processors stacked vertically and connected together — resulting in increased speed and multitasking, more memory and calculating power, better functionality, and wireless connectivity.

The processors are connected vertically by several hundred very thin copper microtubes. These wires pass through tiny openings, called Through-Silicon-Vias (TSV), made in the core of the silicon layer of each chip.

The team had to overcome a number of difficulties, such as the fragility of the copper connections and supports because they are miniaturized to such an extreme degree (about 50 microns in thickness).

The technology will initially be made available to academic research teams for further development, before being commercialized.

See also:
First commercial 3-D chip-making capability announced