High-speed graphene transistors achieve world-record 300 GHz
September 3, 2010
UCLA researchers have fabricated the fastest graphene transistor to date, using a new fabrication process with a nanowire as a self-aligned gate.
Self-aligned gates are a key element in modern transistors, which are semiconductor devices used to amplify and switch electronic signals. Gates are used to switch the transistor between various states, and self-aligned gates were developed to deal with problems of misalignment encountered because of the shrinking scale of electronics.
“This new strategy overcomes two limitations previously encountered in graphene transistors,” professor of chemistry and biochemistry Xiangfeng Duan said. “First, it doesn’t produce any appreciable defects in the graphene during fabrication, so the high carrier mobility is retained. Second, by using a self-aligned approach with a nanowire as the gate, the group was able to overcome alignment difficulties previously encountered and fabricate very short-channel devices with unprecedented performance.”
These advances allowed the team to demonstrate the highest speed graphene transistors to date, with a cutoff frequency up to 300 GHz — comparable to the very best transistors from high-electron mobility materials such gallium arsenide or indium phosphide.
Graphene, a one-atom-thick layer of graphitic carbon, has great potential to make electronic devices such as radios, computers and phones faster and smaller. With the highest known carrier mobility — the speed at which electronic information is transmitted by a material — graphene is a good candidate for high-speed radio-frequency electronics. High-speed radio-frequency electronics may also find wide applications in microwave communication, imaging and radar technologies.
Funding for this research came from the National Science Foundation and the National Institutes of Health.
More info: UCLA news
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Comments (2)
by Vincent
Another serious step forward towards the Singularity.
by LaboriousCretin
Nice but how long of a time frame befor we see them. I’m just glad we have 12 core chip’s. For a 3X3 logic simulation and 3 cores for bridge work transfering and pipe work modifications. 12 core silicon at 5-10GHz. is enough to start and work on for now, as the cluster kernel is made for good level A.I. and rendering to. 0,1,V V= variable string from a micro cache on chip when they start to make them rather than emulate them like now.