IBM researchers develop new technique for integrating ‘III-V’ materials onto silicon wafers

A breakthrough that may allow for an extension to Moore’s Law
June 10, 2015

Scanning electron microscope images of single crystal structures fabricated using template-assisted selective epitaxy. For better visibility, the silicon is colored in green, and the compound semiconductor in red. (credit: H. Schmid/IBM)

A team of IBM researchers in Zurich, Switzerland with support from colleagues in Yorktown Heights, New York has developed a relatively simple, robust and versatile process for growing crystals made from compound semiconductor materials. The new method will allow the materials to be integrated onto silicon wafers — an important step toward making future computer chips that will allow integrated circuits to continue shrinking in size and cost, even as they increase in performance.

Appearing this week on the cover of the journal Applied Physics Letters in an open-access article, the finding may allow for an extension to Moore’s Law. “We need better performing transistors as we continue down-scaling, and transistors based on silicon won’t give us improvements anymore,” said Heinz Schmid, a researcher with IBM Research GmbH at Zurich Research Laboratory in Switzerland and the lead author on the paper.

For consumers, extending Moore’s Law will mean continuing the trend of new computer devices having increasing speed and bandwidth at reduced power consumption and cost. The new technique may also impact photonics on silicon, with active photonic components integrated seamlessly with electronics for greater functionality.

Integrating new semiconductor materials with silicon

The IBM team fabricated single crystal nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3-D stacked nanowires, all made with “III–V” materials. Made from alloys of indium, gallium and arsenide, III-V semiconductors are seen as a possible future material for computer chips, but only if they can be successfully integrated onto silicon.

As ExtremeTech explains, “III-V semiconductors (alloys made from metals in old groups III and V) have long been known as a potential replacement for silicon in CMOS transistors. III-V semiconductors, such as indium gallium arsenide (InGaAs), have much higher electron mobility than silicon, and can thus be fashioned into faster, smaller, and lower-power transistors. Compound semiconductors, as they are known, are already used in high-performance settings — such as military radio transceivers — but they’ve never made the leap to consumer products, due to production cost, defect density, and other factors.”

The new crystals were grown using an approach called template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition, which basically starts from a small area and evolves into a much larger, defect-free crystal. This approach allowed them to lithographically define oxide templates and fill them via epitaxy, in the end making nanowires, cross junctions, nanostructures containing constrictions and 3-D stacked nanowires using the already established scaled processes of Si technology.

“What sets this work apart from other methods is that the compound semiconductor does not contain detrimental defects, and that the process is fully compatible with current chip fabrication technology,” said Schmid. “Importantly the method is also economically viable.”

He added that more development will be required to achieve the same control over performance in III-V devices as currently exists for silicon. But the new method is the key to actually integrating the stacked materials on the silicon platform, Schmid said.


Abstract of Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructurescontaining constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements onInAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.