Intel introduces 3-D transistor design for 22-nm chips
May 5, 2011
Intel announced today that a new 3-D transistor design, called Tri-Gate, has gone into high-volume manufacturing at the 22-nanometer (nm) node in an Intel chip codenamed “Ivy Bridge.”
“The transition to 3-D Tri-Gate transistors sustains the pace of technology advancement, fueling Moore’s Law for years to come,” says Intel.
The new transistor design is called a Finfet (fin field-effect transistor), based around a fin of silicon that rises above the surface of the chip, providing more conductive area.
The traditional “flat” two-dimensional planar gate is replaced with a thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin — two on each side and one across the top — rather than just one on top, as is the case with the 2-D planar transistor.
The additional control enables as much transistor current flowing as possible when the transistor is in the “on” state (for performance), and as close to zero as possible when it is in the “off” state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance).
Intel says the 22nm 3-D Tri-Gate transistors provide up to 37 percent performance increase at low voltage, compared to Intel’s current 32nm planar transistors. This gain means that they are “ideal for use in small handheld devices, which operate using less energy to switch back and forth.”
Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32nm chips.
According to The New York Times, “Industry executives and analysts have said that Intel is likely to have a lead of a full generation over its rivals in the shift to 3-D transistors, which will give Intel a clear speed advantage, but possibly less control over power consumption than alternative approaches.”