Model for testing transistor reliability
December 9, 2004 | Source: KurzweilAI
Purdue University researchers have created a unified model for predicting the reliability of new designs for silicon transistors.
The method can be used to simultaneously evaluate the reliability of two types of transistors essential for CMOS computer chips and accurately predict how new designs for both types of transistors will degrade over time.
The model describes the rate at which silicon-hydrogen bonds break and how they “repair” themselves. It could be particularly useful in testing the reliability of designs for silicon-based chips that use nanotechnology to create smaller and more compact transistors than exist in today’s integrated circuits.