Silicon Device Scaling to the Sub-10-nm Regime

December 20, 2004 | Source: Science Magazine

In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths below 10 nanometers (current gate lengths in chips are about 50 nm).

Technologies being pursued include device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways; improvement in device speed by enhancing the mobility of charge carriers; using strain engineering; and different crystal orientations.