Silicon nanocrystals break miniaturization barrier for memory chips
September 1, 2010
Rice University scientists have created the first two-terminal memory chips that use only silicon to generate nanocrystal wires as small as 5 nanometers — far smaller than circuitry in even the most advanced computers and electronic devices. The technology breakthrough promises to extend the limits of miniaturization subject to Moore’s Law, and should be easily adaptable to nanoelectronic manufacturing techniques.
Jun Yao, a graduate student in Rice Professor James Tour’s lab, confirmed his idea when he sandwiched a layer of silicon oxide, an insulator, between semiconducting sheets of polycrystalline silicon that served as the top and bottom electrodes.
Applying a charge to the electrodes created a conductive pathway by stripping oxygen atoms from the silicon oxide and forming a chain of nano-sized silicon crystals. Once formed, the chain can be repeatedly broken and reconnected by applying a pulse of varying voltage.
“The beauty of it is its simplicity,” said Tour, Rice’s T.T. and W.F. Chao Chair in Chemistry as well as a professor of mechanical engineering and materials science and of computer science. That, he said, will be key to the technology’s scalability. Silicon oxide switches or memory locations require only two terminals, not three (as in flash memory), because the physical process doesn’t require the device to hold a charge.
It also means layers of silicon-oxide memory can be stacked in tiny but capacious three-dimensional arrays. “I’ve been told by industry that if you’re not in the 3-D memory business in four years, you’re not going to be in the memory business. This is perfectly suited for that,” Tour said.
Silicon-oxide memories are compatible with conventional transistor manufacturing technology, said Tour. “Manufacturers feel they can get pathways down to 10 nanometers. Flash memory is going to hit a brick wall at about 20 nanometers. But how do we get beyond that? Well, our technique is perfectly suited for sub-10-nanometer circuits,” he said.
Austin tech design company PrivaTran is already bench-testing a silicon-oxide chip with 1,000 memory elements, built in collaboration with the Tour lab. “We’re real excited about where the data is going here,” said PrivaTran CEO Glenn Mortland, who is using the technology in several projects supported by the Army Research Office, National Science Foundation, Air Force Office of Scientific Research, and the Navy Space and Naval Warfare Systems Command Small Business Innovation Research (SBIR) and Small Business Technology Transfer programs.
Silicon-oxide circuits feature high on-off ratios (>105) , excellent endurance (104 write-erase cycles) and fast switching (<100 nanoseconds). They will also be resistant to radiation, which should make them suitable for military and NASA applications. “It’s clear there are lots of radiation-hardened uses for this technology,” Mortland said.
Silicon oxide also works in reprogrammable gate arrays being built by NuPGA, a company formed last year through collaborative patents with Rice University. NuPGA’s devices will assist in the design of computer circuitry based on vertical arrays of silicon oxide embedded in “vias,” the holes in integrated circuits that connect layers of circuitry. Such rewritable gate arrays could drastically cut the cost of designing complex electronic devices.
The David and Lucille Packard Foundation, the Texas Instruments Leadership University Fund, the National Science Foundation, PrivaTran and the Army Research Office SBIR supported the research.
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