IBM scientists achieve storage-memory breakthrough with PCM

PCM combines speed of DRAM and non-volatility of flash, providing fast, easy storage for the exponential growth of data from mobile devices, the Internet of Things, and cloud computing
May 16, 2016

For the first time, scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). In this photo, the experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip, serving as a characterization vehicle in 90 nm CMOS baseline technology. (credit: IBM Research)

Scientists at IBM Research have demonstrated — for the first time (today, May 17), at the IEEE International Memory Workshop in Paris — reliably storing 3 bits of data per cell in a 64k-cell array in a memory chip*, using a relatively new memory technology known as phase-change memory (PCM). Previously, scientists at IBM and elsewhere successfully demonstrated the ability to store only 1 bit per cell in PCM.

The current memory landscape includes DRAM, hard disk drives, and flash. But in the last several years, PCM has attracted the industry’s attention as a potential universal memory technology based on its combination of read/write speed, endurance, non-volatility and density. For example, PCM doesn’t lose data when powered off, unlike DRAM, and the technology can endure at least 10 million write cycles, compared to an average flash USB stick, which tops out at 3,000 write cycles.

IBM suggests this research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the Internet of Things.

Scientists have long been searching for a universal, non-volatile memory technology with performance far superior to flash — today’s most ubiquitous non-volatile memory technology. The benefits of such a memory technology would allow computers and servers to boot instantaneously and would significantly enhance the overall performance of IT systems. A promising contender is PCM, which can write and retrieve data 100 times faster than Flash and enable high storage capacities, and like flash, not lose data when the power is turned off. Unlike flash, PCM is also very durable and can endure at least 10 million write cycles, compared to current enterprise-class flash at 30,000 cycles or consumer-class flash at 3,000 cycles. While 3,000 cycles will outlive many consumer devices, 30,000 cycles are orders of magnitude too low to be suitable for enterprise applications. (credit: IBM Research)

IBM scientists envision standalone PCM as well as hybrid applications that combine PCM and flash storage, with PCM as an extremely fast cache. For example, a mobile phone’s operating system could be stored in PCM, enabling the phone to launch in a few seconds. In the enterprise space, entire databases could be stored in PCM for blazing fast query processing in time-critical online applications, such as financial transactions.

Machine learning algorithms using large datasets will also see a speed boost by reducing the latency overhead when reading the data between iterations.

How PCM Works: answering the grand challenge of combining properties of DRAM and flash

PCM materials exhibit two stable states: the amorphous (without a clearly defined structure) and crystalline (with structure) phases (low and high electrical conductivity, respectively).

To store a “0″ or a “1″ bit on a PCM cell, a high or medium electrical current is applied to the material. A “0″ can be programmed to be written in the amorphous phase and a “1″ in the crystalline phase, or vice versa. Then to read the bit back, a low voltage is applied. This is how re-writable (but slower) Blu-ray discs** store videos.

Phase-change memory (PCM) is one of the most promising candidates for next-generation non-volatile memory technology. The cross-sectional tunneling electron microscopy (TEM) image of a mushroom-type PCM cell is shown in this photo. The cell consists of a layer of phase-change material, such as germanium antimony telluride (GST), sandwiched between a bottom and a top electrode. In this architecture, the bottom electrode has a radius (denoted as rE ) of approx. 15 nm and is fabricated by sub-lithographic means. The top electrode has a radius in excess of 100 nm and the thickness of the phase change layer is approx. 100 nm. A transistor or a diode is typically employed as the access device. (credit: IBM Research — Zurich)

“Phase change memory is the first instantiation of a universal memory with properties of both DRAM and flash, thus answering one of the grand challenges of our industry,” said Haris Pozidis, PhD., an author of the workshop paper and the manager of non-volatile memory research at IBM Research–Zurich. “Reaching 3 bits per cell is a significant milestone because at this density, the cost of PCM will be significantly less than DRAM and closer to flash.”

To achieve multi-bit storage, IBM scientists have developed two innovative enabling technologies: a set of drift-immune cell-state metrics and drift-tolerant coding and detection schemes***. “Combined, these advancements address the key challenges of multi-bit PCM, including drift, variability, temperature sensitivity, and endurance cycling,” said IBM Fellow Evangelos Eleftheriou, PhD.

IBM scientists have also demonstrated, for the first time, phase-change memory attached to POWER8-based servers.

* At elevated temperatures and after 1 million endurance cycles.

*** “Blu-ray Disc” is owned by the Blu-ray Disc Association (BDA)

*** More specifically, the new cell-state metrics measure a physical property of the PCM cell that remains stable over time, and are thus insensitive to drift, which affects the stability of the cell’s electrical conductivity with time. To provide additional robustness of the stored data in a cell over ambient temperature fluctuations, a novel coding and detection scheme is employed. This scheme adaptively modifies the level thresholds that are used to detect the cell’s stored data so that they follow variations due to temperature change. As a result, the cell state can be read reliably over long time periods after the memory is programmed, thus offering non-volatility.

The experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a four-bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90 nm CMOS baseline technology.


IBM Research | IBM Scientists Achieve Storage Memory Breakthrough


Abstract of Multilevel-Cell Phase Change Memory: A Viable Technology

In order for any non-volatile memory (NVM) to be considered a viable technology, its reliability should be verified at the array level. In particular, properties such as high endurance and at least moderate data retention are considered essential. Phase-change memory (PCM) is one such NVM technology that possesses highly desirable features and has reached an advanced level of maturity through intensive research and development in the past decade. Multilevel-cell (MLC) capability, i.e., storage of two bits per cell or more, is not only desirable as it reduces the effective cost per storage capacity, but a necessary feature for the competitiveness of PCM against the incumbent technologies, namely DRAM and Flash memory. MLC storage in PCM, however, is seriously challenged by phenomena such as cell variability, intrinsic noise, and resistance drift. We present a collection of advanced circuit-level solutions to the above challenges, and demonstrate the viability of MLC PCM at the array level. Notably, we demonstrate reliable storage and moderate data retention of 2 bits/cell PCM, on a 64 k cell array, at elevated temperatures and after 1 million SET/RESET endurance cycles. Under similar operating conditions, we also show feasibility of 3 bits/cell PCM, for the first time ever.

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