Micron readies hybrid memory cube for debut

January 18, 2013

Hybrid Memory Cube (credit: Micron Technology)

The next-generation memory-maker Micron Technology‘s Hybrid Memory Cube (HMC) technology is a multi-chip module (MCM) that aims to address one of the biggest challenges in high performance computing: scaling the memory wall, HPC Wire reports.

Memory architectures haven’t kept pace with the bandwidth requirements of multicore processors. As microprocessor speeds out-accelerated DRAM memory speeds, a bottleneck developed that is referred to as the memory wall. Stacked memory applications, however, enable higher memory bandwidth.

The Hybrid Memory Cube (HMC) is a new 3D memory architecture that combines a high-speed logic layer with a stack of through-silicon-via (TSV) bonded memory die that enables impressive advantages over current technology.

According to company figures, a single HMC offers a 15x performance increase and uses 70 percent less energy per bit when compared to DDR3 memory, and takes up 90 percent less space than today’s RDIMMs. The Cube is also scalable per application, which is not possible with DDR3 and DDR4. System designers have the option of employing the HMC as near memory for best performance or in a scalable module form factor, as far memory, for optimum power efficiency.

Judging by the degree and caliber of community involvement, Micron’s HMC technology represents a real breakthrough in how memory is used. In October 2011, Micron together with Samsung Electronics Co., Ltd., formed the Hybrid Memory Cube Consortium, tasked with developing an open industry standard that facilitates HMC integration into a wide variety of systems, platforms and applications.

The consortium is managed by a group of ten developers (Altera, ARM, HP, IBM, Micron, Microsoft, Open Silicon, Samsung, SK Hynix, and Xilinx), which have equal voting power on the final specification, along with an additional 75 adopters. The members are currently reviewing a draft specification, scheduled to be released next month, that details the communication interface between the Cube and the processor — CPU or GPU or FPGA.

Speaking to the initial set of targeted applications, the driving body notes that the “Hybrid Memory Cube represents the key to extending network system performance to push through the challenges of new 100G and 400G infrastructure growth. Eventually, HMC will drive exascale CPU system performance growth for next generation HPC systems.”

If all goes as planned, the Hybrid Memory Cube will be in full production at the end of this year or early 2014.

The first couple of HMC implementations will be straight DRAM, but Micron and others are researching alternative memory combinations, for example multi-memory stacks that employ NAND flash and DRAM.

Still a year away from production, pricing for Cube products has not been announced, but early adopters should expect to pay a premium for the benefits of increased performance, power efficiency and space savings. The exascale community, in particular, will be paying close attention. If they’re to realize their goal of a 10^18 FLOPS machine within a 20MW power envelope, they’ll need all the help they can get.